//
// Created by 15255 on 25-7-14.
//

#ifndef DART_F4_ICM_IMU_DEFINE_H
#define DART_F4_ICM_IMU_DEFINE_H

#include "main.h"

//register
#define DEVICE_ID_REG                                       0x75
#define DEVICE_CONFIG_REG                                   0x11
#define INT_CONFIG_REG                                      0x14
#define FIFO_CONFIG_REG                                     0x16
#define FIFO_CONFIG1_REG                                    0x5F
#define FIFO_CONFIG2_REG                                    0x60
#define FIFO_CONFIG3_REG                                    0x61
#define INT_SOURCE0_REG                                     0x65
#define REG_BANK_SEL_REG                                    0x76
#define GYRO_CONFIG0_REG                                    0x4F
#define ACCEL_CONFIG0_REG                                   0x50
#define PWR_MGMT0_REG                                       0x4E
#define FIFO_COUNTH_REG                                     0x2E
#define FIFO_COUNTL_REG                                     0x2F
#define FIFO_DATA_REG                                       0x30
#define OFFSET_USER0_REG                                    0x77
#define OFFSET_USER1_REG                                    0x78
#define OFFSET_USER2_REG                                    0x79
#define OFFSET_USER3_REG                                    0x7A
#define OFFSET_USER4_REG                                    0x7B
#define OFFSET_USER5_REG                                    0x7C
#define OFFSET_USER6_REG                                    0x7D
#define OFFSET_USER7_REG                                    0x7E
#define OFFSET_USER8_REG                                    0x7F


//VARS
#define DEVICE_CONFIG_SOFT_RESET                            0x01

#define INT_CONFIG_INT2_MODE_PLUSE_MODE                     0x00
#define INT_CONFIG_INT2_MODE_LATCHED_MODE                   (1 << 5)
#define INT_CONFIG_INT2_DRIVE_CIRCUIT_OPEN_DRAIN            0x00
#define INT_CONFIG_INT2_DRIVE_CIRCUIT_PUSH_PULL             (1 << 4)
#define INT_CONFIG_INT2_POLARITY_ACTIVE_LOW                 0x00
#define INT_CONFIG_INT2_POLARITY_ACTIVE_HIGH                (1 << 3)
#define INT_CONFIG_INT2_MODE_PLUSE_MODE                     0x00
#define INT_CONFIG_INT1_MODE_LATCHED_MODE                   (1 << 2)
#define INT_CONFIG_INT1_DRIVE_CIRCUIT_OPEN_DRAIN            0x00
#define INT_CONFIG_INT1_DRIVE_CIRCUIT_PUSH_PULL             (1 << 1)
#define INT_CONFIG_INT1_POLARITY_ACTIVE_LOW                 0x00
#define INT_CONFIG_INT1_POLARITY_ACTIVE_HIGH                (1 << 0)

#define FIFO_CONFIG_FIFO_MODE_BYPASS                        0x00
#define FIFO_CONFIG_FIFO_MODE_STREAM                        0x40
#define FIFO_CONFIG_FIFO_MODE_STOP_ON_FULL                  0x20


#define REG_BANK_SEL_0                                      0x00
#define REG_BANK_SEL_1                                      0x01
#define REG_BANK_SEL_2                                      0x02
#define REG_BANK_SEL_3                                      0x03
#define REG_BANK_SEL_4                                      0x04

#define INT_SOURCE0_UI_FSYNC_INT1_EN_ROUTED                 (1 << 6)
#define INT_SOURCE0_PLL_RDY_INT1_EN_ROUTED                  (1 << 5)
#define INT_SOURCE0_RESET_DONE_INT1_EN_ROUTED               (1 << 4)
#define INT_SOURCE0_UI_DRDY_INT1_EN_ROUTED                  (1 << 3)
#define INT_SOURCE0_FIFO_THS_INT1_EN_ROUTED                 (1 << 2)
#define INT_SOURCE0_FIFO_FULL_INT1_EN_ROUTED                (1 << 1)
#define INT_SOURCE0_UI_AGC_RDY_INT1_EN_ROUTED               (1 << 0)

#define FIFO_CONFIG1_RESUME_PARTIAL_RD_TRUE                 (1 << 6)
#define FIFO_CONFIG1_WM_GT_TH                               (1 << 5)
#define FIFO_CONFIG1_HIRES_EN                               (1 << 4)
#define FIFO_CONFIG1_TMST_FSYNC_EN                          (1 << 3)
#define FIFO_CONFIG1_TEMP_EN                                (1 << 2)
#define FIFO_CONFIG1_GYRO_EN                                (1 << 1)
#define FIFO_CONFIG1_ACCEL_EN                               (1 << 0)

#define GYRO_CONFIG0_FS_SEL_2000                            0x00
#define GYRO_CONFIG0_FS_SEL_1000                            (1 << 5)
#define GYRO_CONFIG0_FS_SEL_500                             (1 << 6)
#define GYRO_CONFIG0_FS_SEL_250                             (1 << 5) | (1 << 6)
#define GYRO_CONFIG0_FS_SEL_125                             (1 << 7)
#define GYRO_CONFIG0_FS_SEL_62_5                            (1 << 7) | (1 << 5)
#define GYRO_CONFIG0_FS_SEL_31_25                           (1 << 7) | (1 << 6)
#define GYRO_CONFIG0_FS_SEL_15_625                          (1 << 7) | (1 << 6) | (1 << 5)

#define GYRO_CONFIG0_ODR_32K                                (1 << 0)
#define GYRO_CONFIG0_ODR_16K                                (1 << 1)
#define GYRO_CONFIG0_ODR_8K                                 (1 << 1) | (1 << 0)
#define GYRO_CONFIG0_ODR_4K                                 (1 << 2)
#define GYRO_CONFIG0_ODR_2K                                 (1 << 2) | (1 << 0)
#define GYRO_CONFIG0_ODR_1K                                 (1 << 2) | (1 << 1)
#define GYRO_CONFIG0_ODR_200                                (1 << 2) | (1 << 1) | (1 << 0)
#define GYRO_CONFIG0_ODR_100                                (1 << 3)
#define GYRO_CONFIG0_ODR_50                                 (1 << 3) | (1 << 0)

#define ACCEL_CONFIG0_FS_SEL_16G                            0x00
#define ACCEL_CONFIG0_FS_SEL_8G                             (1 << 5)
#define ACCEL_CONFIG0_FS_SEL_4G                             (1 << 6)
#define ACCEL_CONFIG0_FS_SEL_2G                             (1 << 5) | (1 << 6)

#define ACCEL_CONFIG0_ODR_32K                               (1 << 0)
#define ACCEL_CONFIG0_ODR_16K                               (1 << 1)
#define ACCEL_CONFIG0_ODR_8K                                (1 << 1) | (1 << 0)
#define ACCEL_CONFIG0_ODR_4K                                (1 << 2)
#define ACCEL_CONFIG0_ODR_2K                                (1 << 2) | (1 << 0)
#define ACCEL_CONFIG0_ODR_1K                                (1 << 2) | (1 << 1)

#define PWR_MGMT0_TEMP_ENABLE                               0x00
#define PWR_MGMT0_TEMP_DISABLE                              (1 << 5)
#define PWR_MGMT0_IDLE                                      (1 << 4)
#define PWR_MGMT0_GYRO_MODE_OFF                             0x00
#define PWR_MGMT0_GYRO_MODE_STANDBY                         (1 << 2)
#define PWR_MGMT0_GYRO_MODE_LN                              (1 << 3) | (1 << 2)
#define PWR_MGMT0_ACCEL_MODE_OFF                            0x00
#define PWR_MGMT0_ACCEL_MODE_LP                             (1 << 1)
#define PWR_MGMT0_ACCEL_MODE_LN                             (1 << 0) | (1 << 1)

#define DEVICE_ID                                           0x47

#endif //DART_F4_ICM_IMU_DEFINE_H
